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Features
* Utilizes the ARM7TDMITM ARM Thumb Processor Core
- High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE (In-circuit Emulation) 2K Bytes Internal RAM Fully-programmable External Bus Interface (EBI) - Maximum External Address Space of 64M Bytes - Up to 8 Chip Selects - Software Programmable 8/16-bit External Data Bus Multi-processor Interface (MPI) - High-performance External Processor Interface - 512 x 16-bit Dual-port RAM 8-channel Peripheral Data Controller 8-level Priority, Individually Maskable, Vectored Interrupt Controller - 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request 58 Programmable I/O Lines 6-channel 16-bit Timer/Counter - 6 External Clock Inputs - 2 Multi-purpose I/O Pins per Channel 3 USARTs - 2 Dedicated Peripheral Data Controller (PDC) Channels per USART - Support for Up to 9-bit Data Transfers Master/Slave SPI Interface - 2 Dedicated Peripheral Data Controller (PDC) Channels - 8- to 16-bit Programmable Data Length - 4 External Slave Chip Selects Programmable Watchdog Timer Power Management Controller (PMC) - CPU and Peripherals Can Be Deactivated Individually IEEE 1149.1 JTAG Boundary-scan on All Active Pins Fully Static Operation: 0 Hz to 25 MHz (12 MHz at 1.8V) 1.8V to 3.6V Core Operating Voltage Range 2.7V to 5.5V I/O Operating Voltage Range -40C to +85C Operating Temperature Range Available in a 176-lead TQFP Package
* *
* * * * * * *
AT91 ARM(R) Thumb(R) Microcontrollers AT91M63200 Summary
* * * * * * * *
Description
The AT91M63200 is a member of the Atmel AT91 16/32-bit microcontroller family which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based MCU family also features Atmel's high-density, in-system programmable, nonvolatile memory technology. The AT91M63200 has a direct connection to off-chip memory, including Flash, through the External Bus Interface. The Multi-processor Interface (MPI) provides a high-performance interface with an external coprocessor or a high bandwidth peripheral. The AT91M63200 is manufactured using the Atmel high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, a multi-processor interface and a wide range of peripheral functions on a monolithic chip, the AT91M63200 provides a highly-flexible and cost-effective solution to many computeintensive multi-processor applications.
Rev. 1028DS-06/00
1
Pin Configuration
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 AT91M63200 GND GND NCS0 NCS1 NCS2 NCS3 NLB/A0 A1 A2 A3 A4 A5 A6 A7 VDDIO GND A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 VDDIO GND A20/CS7 A21/CS6 A22/CS5 A23/CS4 D0 D1 D2 D3 D4 D5 D6 D7 VDDCORE VDDIO Pin 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 AT91M63200 GND GND D8 D9 D10 D11 D12 D13 D14 D15 PB19/TCLK0 PB20/TIOA0 PB21/TIOB0 PB22/TCLK1 VDDIO GND PB23/TIOA1 PB24/TIOB1 PB25/TCLK2 PB26/TIOA2 PB27/TIOB2 PA0/TCLK3 PA1/TIOA3 PA2/TIOB3 PA3/TCLK4 PA4/TIOA4 PA5/TIOB4 PA6/TCLK5 VDDIO GND PA7/TIOA5 PA8/TIOB5 PA9/IRQ0 PA10/IRQ1 PA11/IRQ2 PA12/IRQ3 PA13/FIQ PA14/SCK0 PA15/TXD0 PA16/RXD0 PA17/SCK1 PA18/TXD1/NTRI VDDCORE VDDIO Pin 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 AT91M63200 GND GND PA19 / RXD1 PA20 / SCK2 PA21 / TXD2 PA22 / RXD2 PA23 / SPCK PA24/MISO PA25/MOSI PA26/NPCS0/NSS PA27/NPCS1 PA28/NPCS2 PA29/NPCS3 MPI_A1 VDDIO GND MPI_A2 MPI_A3 MPI_A4 MPI_A5 MPI_A6 MPI_A7 MPI_A8 MPI_A9 MPI_NCS MPI_RNW MPI_BR MPI_BG VDDIO GND MPI_D0 MPI_D1 MPI_D2 MPI_D3 MPI_D4 MPI_D5 MPI_D6 MPI_D7 MPI_D8 MPI_D9 MPI_D10 MPI_D11 VDDCORE VDDIO Pin 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 AT91M63200 GND GND MPI_D12 MPI_D13 MPI_D14 MPI_D15 PB0/MPI_NOE PB1/MPI_NLB PB2/MPI_NUB PB3 PB4 PB5 PB6 PB7 VDDIO GND PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17/MCKO NWDOVF MCKI VDDIO GND PB18/BMS JTAGSEL TMS TDI TDO TCK NTRST NRST NWAIT NOE/NRD NWE/NWR0 NUB/NWR1 VDDCORE VDDIO
2
AT91M63200
AT91M63200
Pin Description
Module Name A0 - A23 D0 - D15 CS4 - CS7 NCS0 - NCS3 NWR0 NWR1 EBI NRD NWE NOE NUB NLB NWAIT BMS MPI_NCS MPI_RNW MPI_BR MPI_BG MPI MPI_NOE MPI_NLB MPI_NUB MPI_A1 - MPI_A9 MPI_D0 - MPI_D15 AIC IRQ0 - IRQ3 FIQ TCLK0 - TCLK5 Timer TIOA0 - TIOA5 TIOB0 - TIOB5 SCK0 - SCK2 USART TXD0 - TXD2 RXD0 - RXD2 SPCK MISO SPI MOSI NSS NPCS0 - NPCS3 PIO WD Clock Reset PA0 - PA29 PB0 - PB27 NWDOVF MCKI MCKO NRST Function Address Bus Data Bus Chip Select Chip Select Lower Byte 0 Write Signal Lower Byte 1 Write Signal Read Signal Write Enable Output Enable Upper Byte Select (16-bit SRAM) Lower Byte Select (16-bit SRAM) Wait Input Boot Mode Select Chip Select Read Not Write Signal Bus Request From External Processor Bus Grant To External Processor Output Enable Lower Byte Select Upper Byte Select Address Bus Data Bus External Interrupt Request Fast External Interrupt Request Timer External Clock Multipurpose Timer I/O Pin A Multipurpose Timer I/O Pin B External Serial Clock Transmit Data Output Receive Data Input SPI Clock Master In Slave Out Master Out Slave In Slave Select Peripheral Chip Select Programmable I/O Port A Programmable I/O Port B Watchdog Timer Overflow Master Clock Input Master Clock Output Hardware Reset Input Type Output I/O Output Output Output Output Output Output Output Output Output Input Input Input Input Input Output Input Input Input Input I/O Input Input Input I/O I/O I/O Output Input I/O I/O I/O Input Output I/O I/O Output Input Output Input Active Level - - High Low Low Low Low Low Low Low Low Low - Low - High High Low Low Low - - - - - - - - - - - - - Low Low - - Low - - Low Schmitt trigger, internal pull-up PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Input after reset Input after reset Open-drain Schmitt trigger Sampled during reset Used in Byte Write option Used in Byte Write option Used in Byte Write option Used in Byte Select option Used in Byte Select option Used in Byte Select option Used in Byte Select option A23 - A20 after reset Comments All valid after reset
3
Pin Description (Continued)
Module Name Function Type Active Level Comments High enables IEEE 1149.1 JTAG Boundary-scan Low enables ARM Standard ICE debug Schmitt trigger, internal pull-up Schmitt trigger, internal pull-up Schmitt trigger, internal pull-up Schmitt trigger, internal pull-up 3V or 5V nominal supply 2.0V or 3V nominal supply Sampled during reset
JTAGSEL
Selects between JTAG and ICE Mode
Input
-
JTAG/ICE
TMS TDI TDO TCK NTRST VDDIO
Test Mode Select Test Data In Test Data Out Test Clock Test Reset Input I/O Power Core Power Ground Tri-state Mode Enable
Input Input Output Input Input Power Power Ground Input
- - - - Low - - - Low
Power Emulation
VDDCORE GND NTRI
Figure 1. Pin Configuration (Top View)
176 1 AT91M63X00 176-Lead TQFP 133 132
44 45 88
89
4
AT91M63200
AT91M63200
Block Diagram
NTRST TMS TDO TDI TCK
Reset
NRST
JTAG
Embedded ICE MPI_A1-MPI_A9 MPI_D0-MPI_D15 MPI_NCS MPI_RNW MPI_BR MPI_BG P I O Internal RAM 2/8K Bytes EBI: External Bus Interface PB0/MPI_NOE PB1/MPI_NLB PB2/MPI_NUB D0-D15 A1-A19 A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NWAIT NCS0-NCS3 A20/CS7 A21/CS6 A22/CS5 A23/CS4 PB18/BMS
ARM7TDMI Core
MCKI PB17/MCKO PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PA9/IRQ0 PA10/IRQ1 PA11/IRQ2 PA12/IRQ3 PA13/FIQ PA14/SCK0 PA15/TXD0 PA16/RXD0 PA17/SCK1 PA18/TXD1/NTRI PA19/RXD1 PA20/SCK2 PA21/TXD2 PA22/RXD2 PA23/SPCK PA24/MISO PA25/MOSI PA26/NPCS0/NSS PA27/NPCS1 PA28/NPCS2 PA29/NPCS3 P I O ASB
Clock
ASB Controller AMBA Bridge AIC: Advanced Interrupt Controller
EBI User Interface
USART0
2 PDC Channels APB 2 PDC Channels 2 PDC Channels PMC: Power Management Controller Chip ID
TC: Timer Counter Block 0 TC0 TC1 TC2 TC: Timer Counter Block 1 TC0 TC1 P I O
MPI: MultiProcessor Interface
PB19/TCLK0 PB22/TCLK1 PB25/TCLK2 PB20/TIOA0 PB21/TIOB0 PB23/TIOA1 PB24/TIOB1 PB26/TIOA2 PB27/TIOB2 PA0/TCLK3 PA3/TCLK4 PA6/TCLK5 PA1/TIOA3 PA2/TIOB3 PA4/TIOA4 PA5/TIOB4 PA7/TIOA5 PA8/TIOB5
USART1
USART2
SPI: Serial Peripheral Interface
2 PDC Channels
TC2
NWDOVF
WD: Watchdog Timer
PIOA: Parallel I/O Controller A
PIOB: Parallel I/O Controller B
5
Architectural Overview
The AT91M63200 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBATM Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The AT91M63200 peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16-Kbyte address space allocated in the upper 3M bytes of the 4-Gbyte address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modifywrite and complex bit manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Controller. The PIO Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO Controller in order to define which peripheral signals are connected with off-chip logic.
The ARM7TDMI processor operates in little-endian mode in the AT91M63200 microcontroller. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are described in detail in the AT91M63200 datasheet. Electrical and mechanical characteristics are documented in the AT91M63200 Electrical Characteristics datasheet. The ARM Standard In-circuit-Emulation debug interface is supported via the ICE port of the AT91M63200 via the JTAG/ICE port when JTAGSEL is low. IEEE JTAG Boundary-scan is supported via the JTAG/ICE port when JTAGSEL is high.
PDC: Peripheral Data Controller
The AT91M63200 has an 8-channel PDC dedicated to the three on-chip USARTs and to the SPI. One PDC channel is connected to the receiving channel and one to the transmitting channel of each peripheral. The user interface of a PDC channel is integrated in the memory space of each USART channel and in the memory space of the SPI. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed data is transferred, an end-of-transfer interrupt is generated by the corresponding peripheral. See the USART section and the SPI section for more details on PDC operation and programming.
Power Supplies
The AT91M63200 has two kinds of power supply pins: * VDDCORE pins, which power the chip core * VDDIO pins, which power the I/O lines This allows core power consumption to be reduced by supplying it with a lower voltage than the I/O lines. The VDDCORE pins must never be powered at a voltage greater than the supply voltage applied to the VDDIO pins. Typical supported voltage combinations are shown in the following table:
Pins VDDCORE VDDIO Typical Supply Voltages 3.0V or 3.3V 5.0V 3.0V or 3.3V 3.0V or 3.3V 2.0V 3.0V or 3.3V
6
AT91M63200
AT91M63200
EBI: External Bus Interface
The EBI generates the signals that control the access to the external memory or peripheral devices. The EBI is fully programmable and can address up to 64M bytes. It has eight chip selects and a 24-bit address bus, the upper four bits of which are multiplexed with a chip select. The 16-bit data bus can be configured to interface with 8or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. The EBI supports different access protocols, allowing single clock cycle memory accesses. The main features are: * External memory mapping * Up to 8 chip select lines * 8- or 16-bit data bus * Byte write or byte select lines * Remap of boot memory * Two different read protocols * Programmable wait state generation * External wait request * Programmable data float time Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high- or low-level sensitive.
PIO: Parallel I/O Controller
The AT91M63200 features 58 programmable I/O lines. 14 pins on the AT91M63200 are dedicated as general-purpose I/O pins. Other I/O lines are multiplexed with on-chip peripheral I/O signals in order to optimize the use of available package pins. The I/O lines are controlled by two separate and identical PIO controllers (PIOA and PIOB). Each PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller (AIC).
USART: Universal Synchronous/Asynchronous Receiver/Transmitter
The AT91M63200 provides three identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: * Programmable baud rate generator * Parity, framing and overrun error detection * Line break generation and detection * Automatic echo, local loopback and remote loopback channel modes * Multi-drop mode: address detection and generation * Interrupt generation * Two dedicated peripheral data controller channels * 5-, 6-, 7-, 8- and 9-bit character length
MPI: Multi-processor Interface
The AT91M63200 features a second bus interface that is dedicated to parallel data exchange with an external processing device. The MPI features a 1-Kbyte dual-port RAM memory and memory access arbitration logic. The ARM processor core and the external processor can both read and write to the dual-port RAM memory.
AIC: Advanced Interrupt Controller
The AT91M63200 has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real-time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor's NFIQ line can only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to IRQ3. An 8-level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources.
SPI: Serial Peripheral Interface
The AT91M63200 features an SPI, which provides communication with external devices in master or slave mode. The SPI has four external chip selects that can be connected to up to 15 devices. The data length is programmable, from 8- to 16-bit. As for the USART, a 2-channel PDC is used to move data directly between memory and the SPI without CPU intervention for maximum real-time processing throughput.
7
TC: Timer/Counter
The AT91M63200 features two identical Timer/Counter blocks, each containing three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions, including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulsewidth modulation. Each Timer/Counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals that can be configured by the user. Each channel drives an internal interrupt signal that can be programmed to generate processor interrupts via the Advanced Interrupt Controller (AIC). Each Timer Counter block features two global registers that act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each Timer/Counter channel, allowing them to be chained.
PMC: Power Management Controller
The Power Management Controller allows optimization of power consumption. The PMC enables/disables the clock inputs to most of the peripherals as well as to the ARM processor core. When the ARM core clock is disabled, the current instruction is processed before the clock is stopped. The clock can be re-enabled by any enabled interrupt or by a hardware reset. When a peripheral clock is disabled, the clock is immediately stopped. When the clock is re-enabled, the peripheral resumes action where it left off. Due to the static nature of the design, the contents of the on-chip RAM and registers for which the clocks are disabled remain unchanged.
SF: Special Function
The AT91M63200 provides registers that implement the following special functions: * Chip identification * RESET status
WD: Watchdog Timer
The AT91M63200 features an internal watchdog timer, which can be used to guard against system lock-up if the software becomes trapped in a deadlock.
8
AT91M63200
AT91M63200
Ordering Information
Max Speed (MHz) 25 12 Operating Power Supply Range 2.7V to 3.6V (Core) 2.7V to 5.5V (I/Os) 1.8V to 3.6V (Core) 2.7V to 3.6V (I/Os) Ordering Code AT91M63200-25AI 2K AT91M63200-12AI-1.8 TQFP 176 Industrial (-40C to 85C) RAM (Bytes) Package Operating Temperature Range Industrial (-40C to 85C)
9
Package Outline TQFP 176
Common Dimensions (mm)
Symbol c c1 L L1 R2 R1 S q 1 2 3 A A1 A2 0.05 1.35 1.4 0.08 0.08 0.2 0 0 11 11 12 12 13 13 1.6 0.15 1.45 3.5 7 Min 0.09 0.09 0.45 0.6 1.00 REF 0.2 Nom Max 0.2 0.16 0.75
Tolerances of form and position aaa bbb 0.2 0.2
Lead Count Dimensions
Pin Count 176 D/E BSC 26.0 D1/E1 BSC 24.0 b Min 0.17 Nom 0.22 Max 0.27 Min 0.17 b1 Nom 0.2 Max 0.23 e BSC 0.50 ccc 0.10 ddd 0.08
10
AT91M63200
AT91M63200
Package Drawing
aaa
bbb
PIN 1
2 S
ccc
3 ddd
R1
R2 0.25
c
c1
1 L1
11
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1028DS-06/00/0M

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